Digital Beam Forming for SAR System

Evatronix takes part in the FP7 research program DIFFERENT ( aimed at developing the novel architecture of multi-static SAR (Synthetic Aperture Radar) system. It is based on the distributed use of several receiver and transmitter units deployed on the number of low-cost satellites. In such systems the performance gain could be obtained by using multi-antenna beamforming.

Evatronix was responsible for the implementation of digital beamforming (DBFN) baseband processor realizing the main processing of the multi-static SAR data obtained over multiple antenna inputs. A novel hardware architecture for DBFN processing was developed. Finally, Evatronix designed the DBFN processor as an ASIC. These processors interface to 60 ADCs of 12-bit data width and 210 MHz sampling frequency.

Our team focused on:

  • system requirements and architecture definitione
  • RTL design and verification
  • FPGA prototyping
  • radiation hardening of the ASIC layout for space application was outsourced to third party
  • high-speed PCB design and manufacturing
  • sub-system and system integration and testing

IoT system for environment monitoring

This device and accompanying software system is yet to be launched to the market and its details are covered by NDA, but we may reveal some information on the Internet-of-Things application we recently developed. This system encompasses:

  • smart-metering embedded system equipped with
  • environmental sensors
  • signal conditioning and digital signal processing
  • wireless interfaces (LTE/GSM, Wi-Fi, Bluetooth) and GPS receiver
  • web server enabling connection of multiple devices
  • web application for monitoring and processing the measured values
  • mobile application for device configuration and data read-out
  • by means of smartphone
IoT 1

High density, high performance PCB

The aforementioned EB8 board design (see section SOLUTIONS) was a challenging PCB layout experience that required:

  • 20 layers PCB
  • use of two large Xilinx Virtex-7 and Virtex-6 FPGA chips
  • (1761 pins)
  • use of on-chip GTX Transceivers (up to 12.5 Gb/s)
  • DDR3 SODIMM interface
  • PCI Express interface
  • differential SMA clock inputs
  • JTAG header
  • user LEDs and GPIOs
  • high-speed, high-density expansion connectors
High_desity 2

Rigid-Flex PCB

To meet the unusual packaging needs of one our clients in a sophisticated IoT design, we used a Rigid-Flex PCB technology to achieve:

  • elimination of additional components such as connectors and wires
  • the ability to fit PCB to the tight housing imposed by marketing requirements
  • weight reduction of the entire device
  • shock and vibration resistance
  • higher reliability of the connections between the separate PCB boards