Drukuj

PCIe FPGA-in-the-Loop

Evatronix FIL solution incorporates hardware and software mechanisms to enable fast and efficient verification of HDL designs within the Mathworks’ MATLAB®/Simulink® environment. The FIL supports design co-simulation combining HDL Verifier with a series of FPGA development boards from Evatronix.

Evatronix FIL can be utilized in versatile applications. It supports a rapid prototyping of complex digital circuits in realistic conditions on dedicated hardware platforms, e.g. Evatronix EB7-EB8. The FIL enables the acceleration of HDL code execution thus shortening the verification process in comparison to standard Simulink® co-simulation with HDL simulators. The FIL approach efficiently facilitates the algorithm exploration and the behavioural-level system simulation. A model-based design workflow can be supported with code generation in MATLAB® HDL Coder.

In order to speed-up the co-simulation process Evatronix FIL supports standard PCI Express 2.0 interface between a workstation and the dedicated emulation board. A carefully chosen PCIe interface provides higher data throughput and overall system efficiency as compared to the Ethernet connection. First generation of Evatronix FIL during a co-simulation phase shortens significantly data received and send time compared to the Ethernet. The Upcoming generation of Evatronix FIL will substantially speed up data transfer via PCIe providing an HDL designer with a high performance verification and prototyping tool.

The concept of PCIe FIL is shown on figure nr 1.

The concept of  PCIe FIL

Fig. 1 PCIe FIL Concept

Key benefits over HDL simulator co-simulation:

  • over 50x gain (video_sharpening algorithm)
  • more testecase in less time
  • time for more complex testcase
  • shortening the verification process